Performance Analysis of Different Bit Carry Look Ahead Adder Using VHDL Environment

Adders are some of the most critical data path circuits requiring considerable design effort in order to squeeze out as much performance gain as possible. Various adder structures can be used to execute addition such as serial and parallel structures and most of researches have done research on the design of high-speed, low-area, or lowpower adders. Adders like ripple carry adder, carry select adder, carry look ahead adder, carry skip adder, carry save adder etc exist numerous adder implementations each with good attributes and some drawbacks. This paper focuses on the implementation and simulation of 4-bit, 8-bit and 16-bitt carry look-ahead adder based on Very High Speed Integrated Circuit Hardware Description Language (VHDL) and compared for their performance. The simulation is done using ModelSim SE 6.3f and we have recorded the performance improvements in propagating the carry and generating the sum when compared with the traditional carry look ahead adder designed in the same technology. KeywordsAddition, Carry-Lookahead Adder (CLA), High Performance, VHDL Simulation, ModelSim, Xilinx, FPGA.